10.1 Measuring key transport properties of fet devices  (Page 4/4)

Measurement analysis

Typical v-i characteristics of jfets

Voltage sweeps are a great way to learn about the device. [link] shows a typical plot of drain-source voltage sweeps at various gate-source voltages while measuring the drain current, I _D for a n-channel JFET. The V-I characteristics have four distinct regions. Analysis of these regions can provides critical information about the device characteristics such as the pinch off voltage, V _P , transcunductance gain, g _m , drain-source channel resistance, R _DS , and power dissipation, P _D .

Ohmic region (linear region)

This region is bounded by V _DS <V _P . Here the JFET begins to flow a drain current with a linear response to the voltage, behaving like a variable resistor. In this region the drain-source channel resistance, R _DS is modeled by [link] , where ΔV _DS is the change in drain-source voltage, ΔI _D is the change in drain current, and g _m is the transcunductance gain. Solving for g _m results in [link] .

Saturation region

This is the region where the JFET is completely “ON”. The maximum amount of current is flowing for the given gate-source voltage. In this region the drain current can be modeled by the [link] , where I _D is the drain current, I _DSS is the maximum current, V _GS is the gate-source voltage, and V _P is the pinch off voltage. Solving for the pinch off voltage results in [link] .

Breakdown region

This region is characterized by the sudden increase in current. The drain-source voltage supplied exceeds the resistive limit of the semiconducting channel, resulting in the transistor to break down and flow an uncontrolled current.

Pinch-off region (cutoff region)

In this region the gate-source voltage is sufficient to restrict the flow through the channel, in effect cutting off the drain current. The power dissipation, P _D , can be solved utilizing Ohms law (I = V/R) for any region using [link] .

The p-channel JFET V-I characteristics behave similarly except that the voltages are reversed. Specifically, the pinch off point is reached when the gate-source voltage is increased in a positive direction, and the saturation region is met when the drain-source voltage is increased in the negative direction.

Typical v-i characteristics of mosfets

[link] shows a typical plot of drain-source voltage sweeps at various gate-source voltages while measuring the drain current, I _D for an ideal n-channel enhancement MOSFET. Like JFETs, the V-I characteristics of MOSFETS have distinct regions that provide valuable information about device transport properties.

Ohmic region (linear region)

The n-channel enhanced MOSFET behaves linearly, acting like a variable resistor, when the gate-source voltage is greater than the threshold voltage and the drain-source voltage is greater than the gate-source voltage. In this region the drain current can be modeled by [link] , where I _D is the drain current, V _GS is the gate-source voltage, V _T is the threshold voltage, V _DS is the drain-source voltage, and k is the geometric factor described by [link] , where µ _n is the charge-carrier effective mobility, C _OX is the gate oxide capacitance, W is the channel width, and L is the channel length.

Saturation region

In this region the MOSFET is considered fully “ON”. The drain current for the saturation region is modeled by [link] . The drain current is mainly influenced by the gate-source voltage, while the drain-source voltage has no effect.

Solving for the threshold voltage V _T results in [link] .

Pinch-off region (cutoff region)

When the gate-source voltage, V _GS , is below the threshold voltage V _T the charge carriers in the channel are not available “cutting off” the charge flow. Power dissipation for MOSFETs can also be solved using equation 6 in any region as in the JFET case.

Fet v-i summary

The typical I-V characteristics for the whole family of FETs seen in [link] are plotted in [link] .

From [link] we can see how the doping schemes that lead to enhancement and depletion are displaced along the V _GS axis. In addition, from the plot the ON or OFF state can be determined for a given gate-source voltage, where (+) is positive, (0) is zero, and (-) is negative, as seen in [link] .

Bibliography

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• P. Horowitz and W. Hill, in Art of Electronics, Cambridge University Press, New York, 2 ^nd Edn., 1994.
• Electronics Tutorials, http://www.electronics-tutorials.ws/ (accessed February 2015).
• C. Alexander and M. Sadiku, in Fundamentals of Electric Circuits , McGraw-Hill Education, New York, 4 ^th Edn., 2009.
• Interactive Explanations for Semiconductor Devices, http://www-g.eng.cam.ac.uk/mmg/teaching/linearcircuits/index.html (accessed February 2015).
• D. Neamen, in An Introduction to Semiconductor Devices , McGraw-Hill Education, New York, 1 ^st Edn., 2005.